1. Technical Field
Example embodiments relate to a semiconductor device and erase methods thereof and, more particularly, to a semiconductor device and erase methods, which can reduce the distribution width of the threshold voltages of memory cells.
2. Related Art
A semiconductor device includes a memory cell array including a plurality of memory blocks. Each of the memory blocks includes a plurality of memory cells.
An erase operation of the semiconductor device is performed on a memory block, selected from among the plurality of memory blocks. If the erase operation is performed when the memory cells of the selected memory block are programmed in various states, a distribution of the threshold voltages of the erased memory cells becomes very wide. This is described with reference to the following graph.
FIG. 1 is a graph illustrating threshold voltages of memory cells according to a known erase operation.
Recently, a multi-level cell (MLC) programmed in various levels is chiefly used. Accordingly, the threshold voltages of memory cells included in a memory block have various distributions 10a, 10b, and 10c. An example in which a memory cell is programmed in three states is shown in FIG. 1. In a program state, the first state 10a is a state in which the threshold voltages of memory cells are the lowest, the second state 10b is a state in which the threshold voltages of the memory cells are higher than the first state 10a, and the third state 10c is a state in which the threshold voltages of the memory cells are higher than the second state 10b. If memory cells having different program states as described above are erased, memory cells having the first state 10a attain the erase state 20 earlier than memory cells having the second or the third state 10b or 10c. Accordingly, when the memory cells of the third state 10c are erased, the threshold voltages of memory cells having the first or second state 10a or 10b which have been erased are further lowered because the threshold voltages of the erased memory cells are influenced by an erase pulse. If the threshold voltages 20 of the memory cells of an erased memory block are lowered as described above, the width W1 in the distribution of the threshold voltages is widened. As a result, the time taken to perform a subsequent program operation may be increased.